A 0.18 μm Differential LNA with reduced Power Consumption

This work presents the design of an inductively source degenerated CMOS differential common source cascode Low Noise Amplifier (LNA) operating at 2 GHz frequency. An inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. Another inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and to increase power gain of the cascode transistors in a differential cascode LNA. The proposed design can reduce the power consumption, and increase the power gain of the LNA. The area occupied by the proposed design measured from the layout is observed as 1.111 mm × 1.27 mm. The LNA is designed with the 0.18 μm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors.